Ofensteuerung v1.0: Wemos-Platine 100x100 mit Pumpenrelais 230 V, Thermostat parallel, Strommessung ZMCT103C/ADS1115, MAX6675 Abgas, 3x DS18B20, Servo MG996R, PWM-Pumpe; 2-stufiges Freerouting, ESPHome-Konfig
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#!/usr/bin/env python3
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"""Platzierte Platine (ohne Leiterbahnen) aus design.py erzeugen -> ofensteuerung_unrouted.kicad_pcb"""
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import os, sys, json
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import pcbnew
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HERE = os.path.dirname(os.path.abspath(__file__))
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sys.path.insert(0, HERE)
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from design import PARTS, PROJECT, W, H, MAINS, MAINS_AREA
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REFPOS = {'A1': (81.4, 20.0)}
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FPDIR = '/usr/share/kicad/footprints'
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mm = pcbnew.FromMM
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def V(x, y): return pcbnew.VECTOR2I(mm(x), mm(y))
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symuuids = json.load(open(os.path.join(HERE, 'symuuids.json')))
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board = pcbnew.LoadBoard(os.path.join(HERE, PROJECT + '_template.kicad_pcb')) if False else pcbnew.CreateEmptyBoard()
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board.SetFileName(os.path.join(HERE, PROJECT + '.kicad_pcb'))
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ds = board.GetDesignSettings()
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ds.SetCopperLayerCount(2)
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ns = ds.m_NetSettings
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dnc = ns.GetDefaultNetclass()
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dnc.SetTrackWidth(mm(0.4)); dnc.SetClearance(mm(0.25)); dnc.SetViaDiameter(mm(0.8)); dnc.SetViaDrill(mm(0.4))
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pnc = pcbnew.NETCLASS('Power')
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pnc.SetTrackWidth(mm(0.8)); pnc.SetClearance(mm(0.3)); pnc.SetViaDiameter(mm(1.0)); pnc.SetViaDrill(mm(0.5)); pnc.SetPriority(0)
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ns.SetNetclass('Power', pnc)
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pnc.SetTrackWidth(mm(1.0))
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mnc = pcbnew.NETCLASS('Mains')
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mnc.SetTrackWidth(mm(2.0)); mnc.SetClearance(mm(2.5)); mnc.SetViaDiameter(mm(2.2)); mnc.SetViaDrill(mm(1.0)); mnc.SetPriority(0)
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ns.SetNetclass('Mains', mnc)
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for pat in ('GND', '+5V', '+3V3'):
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ns.SetNetclassPatternAssignment(pat, 'Power')
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for n in MAINS:
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ns.SetNetclassPatternAssignment('/' + n, 'Mains')
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ns.SetNetclassPatternAssignment('unconnected-(K1-*', 'Mains')
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ds.m_TrackMinWidth = mm(0.25); ds.m_MinClearance = mm(0.2); ds.m_CopperEdgeClearance = mm(0.4)
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nets = {}
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POWER = ('GND', '+5V', '+3V3')
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def net(name):
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name = name if (name in POWER or name.startswith('unconnected-')) else '/' + name
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if name not in nets:
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n = pcbnew.NETINFO_ITEM(board, name); board.Add(n); nets[name] = n
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return nets[name]
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for p in PARTS:
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if p.get('board') is False or not p['fp']:
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continue
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lib, name = p['fp'].split(':')
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libpath = os.path.join(HERE, lib + '.pretty') if lib == PROJECT else os.path.join(FPDIR, lib + '.pretty')
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fp = pcbnew.FootprintLoad(libpath, name)
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if fp is None:
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raise SystemExit('fp missing ' + p['fp'])
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fp.SetFPID(pcbnew.LIB_ID(lib, name))
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fp.SetReference(p['ref']); fp.SetValue(p['val'])
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fp.SetPath(pcbnew.KIID_PATH('/' + symuuids[p['ref']]))
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x, y, rot = p['pcb']
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fp.SetPosition(V(x, y))
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fp.SetOrientationDegrees(rot)
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board.Add(fp)
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for pad in fp.Pads():
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n = p['pins'].get(pad.GetNumber())
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if n:
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pad.SetNet(net(n))
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elif pad.GetNumber() and pad.GetNumber() in p['pins']:
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nm = p.get('ncname', {}).get(pad.GetNumber(), '')
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pad.SetNet(net(f"unconnected-({p['ref']}-{nm + '-' if nm else ''}Pad{pad.GetNumber()})"))
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for k in ('Description', 'Bezugsquelle'):
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v = p.get({'Description': 'desc', 'Bezugsquelle': 'mpn'}[k], '')
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if k == 'Description' or v:
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try:
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fld = fp.GetField(k) if fp.HasField(k) else None
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if fld is None:
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fld = pcbnew.PCB_FIELD(fp, fp.GetNextFieldId() if hasattr(fp,'GetNextFieldId') else -1, k); fp.Add(fld)
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fld.SetText(v); fld.SetVisible(False); fld.SetLayer(pcbnew.F_Fab)
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except Exception as e:
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print('field', k, e)
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# Referenz klein, Value auf Fab
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fp.Reference().SetTextSize(V(0.9, 0.9)); fp.Reference().SetTextThickness(mm(0.14))
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fp.Value().SetLayer(pcbnew.F_Fab)
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if p['fp'].split(':')[0] in ('Resistor_THT', 'Diode_THT') or p['fp'].startswith('Capacitor_THT:C_Disc'):
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pads = list(fp.Pads())
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a, b2 = pads[0].GetPosition(), pads[1].GetPosition()
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fp.Reference().SetPosition(pcbnew.VECTOR2I((a.x + b2.x) // 2, (a.y + b2.y) // 2))
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fp.Reference().SetTextAngleDegrees(rot if rot in (0, 90) else rot - 180)
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fp.Reference().SetTextSize(V(0.8, 0.8)); fp.Reference().SetTextThickness(mm(0.13))
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if p['ref'] in REFPOS:
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fp.Reference().SetPosition(V(*REFPOS[p['ref']])); fp.Reference().SetTextAngleDegrees(0)
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if p['ref'] in ('J10',):
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fp.Reference().SetVisible(False)
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if p['fp'].startswith('Connector_Phoenix'):
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npins = len(p['pins']); sgn = 1 if rot == 0 else -1
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fp.Reference().SetPosition(V(x + sgn * 5.08 * (npins - 1) + sgn * 2.6, y + (-2.0 if rot == 180 else 2.0)))
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fp.Reference().SetTextAngleDegrees(0)
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# Platinenumriss mit abgerundeten Ecken
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def seg(a, b):
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s = pcbnew.PCB_SHAPE(board); s.SetShape(pcbnew.SHAPE_T_SEGMENT); s.SetStart(V(*a)); s.SetEnd(V(*b))
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s.SetLayer(pcbnew.Edge_Cuts); s.SetWidth(mm(0.1)); board.Add(s)
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def arc(c, start, ang):
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s = pcbnew.PCB_SHAPE(board); s.SetShape(pcbnew.SHAPE_T_ARC); s.SetCenter(V(*c)); s.SetStart(V(*start))
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s.SetArcAngleAndEnd(pcbnew.EDA_ANGLE(ang, pcbnew.DEGREES_T)); s.SetLayer(pcbnew.Edge_Cuts); s.SetWidth(mm(0.1)); board.Add(s)
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r = 2.0
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seg((r, 0), (W - r, 0)); seg((W, r), (W, H - r)); seg((W - r, H), (r, H)); seg((0, H - r), (0, r))
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arc((W - r, r), (W - r, 0), 90); arc((W - r, H - r), (W, H - r), 90); arc((r, H - r), (r, H), 90); arc((r, r), (0, r), 90)
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# GND-Flächen beidseitig
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def zone(layer, netname, pts, keepout=False):
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z = pcbnew.ZONE(board)
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z.SetLayer(layer)
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if keepout:
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z.SetIsRuleArea(True); z.SetDoNotAllowTracks(True); z.SetDoNotAllowVias(True); z.SetDoNotAllowZoneFills(True)
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z.SetDoNotAllowPads(False); z.SetDoNotAllowFootprints(False)
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ls = pcbnew.LSET(); ls.AddLayer(pcbnew.F_Cu); ls.AddLayer(pcbnew.B_Cu); z.SetLayerSet(ls)
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else:
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z.SetNet(net(netname)); z.SetMinThickness(mm(0.25)); z.SetLocalClearance(mm(0.4))
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z.SetPadConnection(pcbnew.ZONE_CONNECTION_THERMAL); z.SetThermalReliefGap(mm(0.5)); z.SetThermalReliefSpokeWidth(mm(0.6))
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z.SetAssignedPriority(0)
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ol = z.Outline(); ol.NewOutline()
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for (x, y) in pts:
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ol.Append(mm(x), mm(y))
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board.Add(z)
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return z
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for L in (pcbnew.F_Cu, pcbnew.B_Cu):
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zone(L, 'GND', [(0.5, 0.5), (W - 0.5, 0.5), (W - 0.5, H - 0.5), (0.5, H - 0.5)])
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# Antennen-Freifläche unter dem ESP8266-Modul (Antenne zeigt zum oberen Rand)
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zone(pcbnew.F_Cu, None, [(68.6, 1.0), (94.2, 1.0), (94.2, 13.0), (68.6, 13.0)], keepout=True)
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# 230-V-Bereich: keine GND-Fläche (beide Lagen)
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z = pcbnew.ZONE(board); z.SetIsRuleArea(True); z.SetDoNotAllowZoneFills(True); z.SetDoNotAllowTracks(False); z.SetDoNotAllowVias(False)
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z.SetDoNotAllowPads(False); z.SetDoNotAllowFootprints(False); z.SetZoneName('NETZ_230V')
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ls = pcbnew.LSET(); ls.AddLayer(pcbnew.F_Cu); ls.AddLayer(pcbnew.B_Cu); z.SetLayerSet(ls)
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ol = z.Outline(); ol.NewOutline()
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for (x, y) in MAINS_AREA:
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ol.Append(mm(x), mm(y))
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board.Add(z)
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# Kleinspannungs-Stummel aus dem 230-V-Bereich (CT-Sekundärseite, Relaisspule), gesperrt
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def padpos(ref, num):
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for fp in board.GetFootprints():
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if fp.GetReference() == ref:
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for pd in fp.Pads():
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if pd.GetNumber() == num:
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p = pd.GetPosition(); return (pcbnew.ToMM(p.x), pcbnew.ToMM(p.y))
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raise KeyError((ref, num))
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def track(netname, pts, width):
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for a, b in zip(pts, pts[1:]):
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t = pcbnew.PCB_TRACK(board); t.SetStart(V(*a)); t.SetEnd(V(*b)); t.SetWidth(mm(width)); t.SetLayer(pcbnew.F_Cu)
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t.SetNet(net(netname)); t.SetLocked(True); board.Add(t)
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YO = MAINS_AREA[2][1] + 1.0
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vm = padpos('T1', '2'); ca = padpos('T1', '1'); k5 = padpos('K1', '5'); k2 = padpos('K1', '2')
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track('VMID', [vm, (vm[0] - 2.0, vm[1] + 2.0), (vm[0] - 2.0, YO)], 0.4)
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track('CT_A', [ca, (ca[0] + 2.0, ca[1] + 2.0), (ca[0] + 2.0, YO)], 0.4)
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track('+5V', [k5, (k5[0] - 1.5, k5[1] + 1.5), (k5[0] - 1.5, YO)], 1.0)
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track('RELAY_C', [k2, (k2[0] + 1.5, k2[1] + 1.5), (k2[0] + 1.5, YO)], 0.6)
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# Trennlinie 230 V auf dem Bestückungsdruck
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for a, b in (((MAINS_AREA[1][0], 1.5), MAINS_AREA[2]), (MAINS_AREA[2], (1.5, MAINS_AREA[2][1]))):
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s = pcbnew.PCB_SHAPE(board); s.SetShape(pcbnew.SHAPE_T_SEGMENT); s.SetStart(V(*a)); s.SetEnd(V(*b))
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s.SetLayer(pcbnew.F_SilkS); s.SetWidth(mm(0.3)); board.Add(s)
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# Randstreifen: keine Leiterbahnen näher als 0,8 mm am Rand
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for pts in ([(0, 0), (W, 0), (W, 0.8), (0, 0.8)], [(0, H - 0.8), (W, H - 0.8), (W, H), (0, H)],
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[(0, 0), (0.8, 0), (0.8, H), (0, H)], [(W - 0.8, 0), (W, 0), (W, H), (W - 0.8, H)]):
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z = zone(pcbnew.F_Cu, None, pts, keepout=True); z.SetDoNotAllowZoneFills(False)
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# Beschriftung
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def text(t, x, y, size=1.2, layer='F.SilkS', rot=0, bold=False):
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layer = {'F.SilkS': pcbnew.F_SilkS, 'B.SilkS': pcbnew.B_SilkS}[layer]
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s = pcbnew.PCB_TEXT(board); s.SetText(t)
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if layer == pcbnew.B_SilkS: s.SetMirrored(True)
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s.SetPosition(V(x, y)); s.SetLayer(layer)
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s.SetTextSize(V(size, size)); s.SetTextThickness(mm(size * (0.2 if bold else 0.15))); s.SetTextAngleDegrees(rot)
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board.Add(s)
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from design import SILK
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for args in SILK:
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text(*args)
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ns.RecomputeEffectiveNetclasses() if hasattr(ns,'RecomputeEffectiveNetclasses') else None
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board.SynchronizeNetsAndNetClasses(True)
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pcbnew.SaveBoard(os.path.join(HERE, PROJECT + '_unrouted.kicad_pcb'), board)
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print('saved', len(board.GetFootprints()), 'footprints')
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